module gen (
    input           clk_1k,rstn,
    output    reg   q
);

integer count;
always @(posedge clk_1k or negedge rstn) begin
    if (!rstn) begin
        q <= 1'b0;
        count <= 0;
    end else begin
        if (count == 7) begin
            count <= 0;
            q <= 1'b1;
        end else begin
            count <= count + 1;
            case (count)
                0: q <= 1'b0;
                1: q <= 1'b0;
                2: q <= 1'b1;
                3: q <= 1'b1;
                4: q <= 1'b0;
                5: q <= 1'b1;
                6: q <= 1'b0;
                default: q <= 1'bZ;
            endcase
        end
    end
end
endmodule //gen